- New blog series: One SSD Technology a Day
- A SSD Technology a Day (1) – Static Data Rotation
- A SSD Technology a Day (2) – What’s the difference between SLC and MLC?
- A SSD Technology a Day (3) – Program and Erase Cycle (P/E)
- A SSD Technology a Day (4) – Redundant Array of Independent Silicon Elements (RAISE)
- A SSD Technology a Day (5) – Wear Leveling
- A SSD Technology a Day (6) – CacheCade
- A SSD Technology a Day (7) – Intelligent Bad Block Management
- A SSD Technology a Day (8) – eMLC and MLC-HET
One of the limitations of flash memory is that while it can be read or programmed a byte or a word at a time in a random access fashion just like regular RAM, it can only be erased a “block” at a time. This will set all bits in the block to 1 which is the default state for NAND memory.
Writing a byte in flash memory involves 2 steps: Program and Erase (P/E). The block is written to a new cell and the old block needs to be erased.
The programing can be done at cell level (setting it to the “0” state) via a process called tunneling while the floating gate is being flooded with high voltage using the on-chip charge pumps.
Erasing can be done only on an entire block (resetting it to the “1” state), thru high negative voltage pulling the electrons off the floating gate via process called quantum tunneling. Flash memory is divided in erase segments (often called blocks or sectors).
3 Replies to “A SSD Technology a Day (3) – Program and Erase Cycle (P/E)”
Why erase on block why can’t on page and why write to page not on block/eccpage why read on ecc page why not block/page
These are specific to each HW implementation. I was just trying to outline the basic concept